1. Field of the Invention
The present invention relates to a wafer level package and a method of fabricating the same, and more particularly, to a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package.
2. Discussion of Related Art
In general, devices performing specific functions, such as a Radio Frequency (RF) filter, an RF switch, a Microelectromechanical Systems (MEMS) structure and an actuator, which are manufactured in a chip unit, are vulnerable to moisture, particles and high temperature, and thus require separate packaging. The packaging is performed by covering and sealing an upper surface of a device wafer on which a device performing a specific function is formed with a cap having a cavity for accommodating the device.
A wafer level package refers to a device fabricated by sealing and packaging a wafer on which a plurality of devices are formed with a packaging cap formed in a wafer unit before cutting the wafer into unit chips.
FIG. 1 illustrates the structure of a conventional wafer level package.
Referring to FIG. 1, solders 130 are formed between an upper substrate 110 and a lower substrate 120, and the upper and lower substrates 110 and 120 are aligned and bonded by applying heat and pressure in a vacuum or a specific gas, thereby fabricating the conventional wafer level package. Here, an internal device 140 performing a particular function like an MEMS structure is disposed in a cavity formed in the upper substrate 110, sealed by the solders 130, and thus can be protected from outside.
Meanwhile, the upper substrate 110 includes communication lines 150 for exchanging an electrical signal between the internal device 140 and the outside of the package, and the communication lines 150 are formed by a via process penetrating the upper substrate 110. More specifically, the communication lines 150 are formed using a via filling technique of forming a through-hole in a substrate and then filling the hole with a metal. To process the through-holes, silicon deep-Reactive Ion Etching (RIE), a sand blasting technique, a laser processing technique, etc., are used.
However, the via process used to form a communication line penetrating a substrate is costly, amounting to about 30 to 40% of the total fabrication cost, and complicates the process.